1. Field of the Invention
The field of the invention is that of digital signals phase modulated with at least two phase states.
To be more precise the invention concerns a phase synchronization device designed to be integrated into the demodulator stage of a receiver for digital signals of this kind transmitted by successive packets.
2. Description of the Prior Art
A special application of the device of the invention is to TDMA (time division multiple access) modems used in a system of satellite repeaters, for example.
In a system of this kind data is transmitted in frames each made up of a plurality of packets. The corresponding signal is phase modulated and each packet begins with a carrier and timing recovery preamble comprising a specific number of symbols. For each packet received the TDMA modem must acquire phase synchronization before the end of the preamble provided for this purpose and then retain this phase synchronization until the next packet.
The general principle for demodulating a phase modulated digital signal is as follows: the received signal is passed through an intermediate frequency bandpass filter and then split into two components in phase quadrature by multiplying it respectively by the output signal of a local oscillator and by a signal in phase quadrature with the output signal of the local oscillator. Each of these two analog components is filtered and then converted into a digital component by a digital-analog converter.
Thus a succession of pairs of digital components in phase quadrature is received. The problem is to retrieve the symbols transmitted for these successive pairs.
The reasoning employed usually refers to the phase plane in which the theoretical phase states are represented in a first frame of reference and the actual phase states (corresponding to the successive pairs of components in phase quadrature) are shown in a second frame of reference, these two frames of reference having the same origin.
In each frame of reference a phase state is represented by a point whose cartesian coordinates are the phase component and the phase quadrature component.
In the general case of modulation with 2.sup.n phase states the 2.sup.n points corresponding to the 2.sup.n theoretical phase states are, in the first frame of reference, on a common circle centered on the origin of the first frame of reference. The signal is not amplitude modulated and only the phase varies.
These 2.sup.n points constitute the constellation of theoretical phase states of the modulation with 2.sup.n phase states. The 2.sup.n phase values associated with the various points of the constellation are: EQU (2k +1)(.pi./2n), with k .epsilon.[0, 2.sup.n -1]
Each phase state is associated with a symbol comprising n bits.
For example, the constellation of phase states of phase modulation with four phase states (quaternary phase-shift keying--QPSK) comprises four points with respective phases of .pi./4, 3.pi./4, 5.pi./4 and 7.pi./4.
By taking a sufficient number of successive pairs of components in quadrature at the receiving end, there are also obtained 2.sup.n points constituting the constellation of phase states of the received signal, two successive points of this constellation being separated by the same angular distance as two points of the constellation of theoretical phase states.
Although the first and second frames of reference, respectively associated with the constellation of theoretical phase states and the constellation of phase states of the received signal, have the same origin, they can rotate relative to each other because the phase reference (the abscissa axis) of each of the two frames of reference is chosen arbitrarily.
A specific object of the invention is a device for obtaining identical frames of reference. This amounts to choosing the same phase reference of the two frames of reference so that the two constellations are superposed.
Following this phase synchronization, a decision module is used to associate one of the possible 2.sup.n symbols with each pair of components.
There remains an indeterminacy. As the two constellations have rotated relative to each other before they were superposed, it is impossible to determine directly if each symbol associated with a pair of components by the decision module is actually the right symbol.
This indeterminacy is resolved in an ambiguity resolving device on the output side of the decision module.
It therefore seems that a phase synchronization device adapted to be integrated into the demodulator stage of a receiver for digital signals phase modulated with 2.sup.n phase states, where n .gtoreq.1, must comprise a correction module for rotating the constellation of phase states of the received signals relative to the constellation of theoretical phase states in order to eliminate any phase shift. This rotation is conditioned by information representing the phase shift.
A first known solution for synchronizing the phase is to calculate the information representing the phase shift between the two constellations (receive and theoretical) using a phase-locked loop.
This first solution has good noise immunity.
However, it has the major drawback that it cannot ensure fast phase synchronization. This first solution applies exclusively to a signal with a continuous bit rate. The reception and the demodulation of a signal of this kind require only one phase synchronization, at the start of reception, there being no constraint as to the speed of this phase synchronization.
During subsequent reception the very good noise immunity of the phase-locked loop enables the synchronization to be maintained with very good accuracy.
The invention concerns phase synchronization of a digital signal transmitted by successive packets. In other words, in the context of the invention, each packet must be synchronized in phase before a predetermined short time period has elapsed. This short time period corresponds, for example, to a preamble comprising a limited number of symbols. The start of packet synchronization must then be maintained until the next packet.
It is therefore impossible, for reasons of speed, to use the first solution based on the use of a phase-locked loop to resolve the problem arising from phase synchronization of a digital signals transmitted by successive packets.
A second known solution which can resolve this problem of fast synchronization is to use a calculator circuit using the Viterbi algorithm in order to supply the correction module quickly with information representative of the phase shift.
Unlike a phase-locked loop, a circuit of this kind enables fast phase synchronization at the start of each packet.
Nevertheless, this second solution also has a major drawback, namely poor noise immunity leading to a high bit error rate (BER). In other words, although synchronization is achieved quickly this is at the cost of accuracy. This lack of accuracy, characteristic of the viterbi algorithm, is effective over the entire duration of the packet.
An object of the invention is to overcome the various drawbacks of the prior art.
To be more precise, one object of the invention is to provide a phase synchronization device adapted to be integrated into the demodulator stage of a receiver for phase modulated digital signals with at least two phase states, the signal being transmitted by successive packets.
Another object of the invention is to provide a device of this kind which enables fast phase synchronization, the duration of phase synchronization having to be less than a predetermined duration corresponding, for example, to the duration of the preamble of each packet.
Another object of the invention is to provide a device of this kind which enables the fast phase synchronization achieved at the start of the packet to be maintained with good noise immunity (and therefore a low BER) throughout the remaining duration of the packet.
In other words, an object of the invention is to provide a device of this kind enabling fast phase synchronization at the start of a packet with this synchronization retained with good noise immunity (and therefore a low BER) until the end of the packet.